Reducing current supplied to an integrated circuit

ABSTRACT

An integrated circuit of the present invention includes power regulating circuitry for reducing preregulator bias current. In one embodiment, power regulating circuitry includes a two stage preregulator for supplying current to a charge pump and a primary regulator. The first stage includes a high power operational amplifier for quickly establishing substrate bias and other pumped voltages before primary voltage is coupled to the remainder of the integrated circuit. Preregulated and pumped voltages are used to establish a reference voltage for the primary regulator. The second stage preregulator includes a low power series regulator to power the charge pumps and so maintain the reference voltage. When the primary regulator has generated the primary voltage level, the power regulating circuitry couples the primary voltage to the remainder of the integrated circuit and disables the first stage preregulator. Using circuitry and operating methods of the present invention, the total operating and standby current supplied to the integrated circuit no longer includes the bias currents related to the operation of the high power operational amplifier.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a continuation to U.S. patent application No. 08/067,194, filedMay 25, 1993 now U.S. Pat. No. 5,446,367.

FIELD OF THE INVENTION

The present invention relates generally to integrated circuits, and moreparticularly, to integrated circuits that employ on-chip voltageregulation.

BACKGROUND

The typical integrated circuit is designed to connect to a singleexternal supply voltage. Within the integrated circuit several internalvoltages are often used for example to bias the substrate, to powersubcircuits, and to charge circuitry having distributed and parasiticcapacitance. The integrated circuit design, therefore, includes voltageregulators for developing the internal voltages from the singleexternally supplied voltage. Each voltage regulator operates at a givenefficiency, usually in the range of 50 to 80 percent. The lossesinherent in less than 100 percent efficiency are expended as heat. Inaddition, some conventional voltage regulator circuits requirecontinuous current flow for establishing bias voltages. For integratedcircuits including dynamic random access memory, for example, thecurrent drawn from the external voltage supply when the circuit is idleis almost entirely the bias current required for voltage regulation.

FIG. 2 is a functional block diagram of a voltage regulator circuit fora conventional integrated circuit. The externally supplied voltage VCCXon line 142 is input to an initial regulator 110. Initial regulator 110includes a series pass regulator designed to drive high impedance loads.Initial regulator 110 is coupled to preregulator 112 and VCC regulator120. Preregulator 112 and VCC regulator 120 include series passregulators that are physically larger than the regulator used in initialregulator 110. These larger regulators more efficiently pass largercurrents to lower impedance loads than the smaller regulator of initialregulator 110. However, as a consequence of the ability to regulatelarger currents, these larger regulators dissipate more energy as heatand require larger bias currents than a smaller regulator. From 50 to 98percent of the total standby power dissipation of a conventionalintegrated circuit dynamic memory device is dissipated by the circuitperforming the function of preregulator 112. Preregulator 112 in theconventional circuit must be carefully designed.

The design of preregulator 112 is constrained by several design goals.Preregulator 112 should have low impedance drive capability to supportrapid changes in load current supplied to charge pump 118. Secondpreregulator 112 should be located in an area of the integrated circuitwhere power dissipation in the form of heat can be tolerated. As ananalog circuit, preregulator 112 should be located in an area of theintegrated circuit away from digital circuitry so that interferencebetween the analog and digital circuits is minimal. Coupling ofsubstrate currents is one example of unintended coupling that can bereduced by physically separating analog and digital circuits.

In the conventional design of preregulator 112, sophisticated circuitryis employed to avoid underdamped output voltage to charge pump 118 whensupply voltage VCCX or load current to charge pump 118 changes suddenly.Such circuitry conventionally takes the form of an operational amplifierrequiring large bias currents (for example 5 milliamps) to support alarge series pass transistor (for example 10,000 microns by 1.5microns). The complexity of the operational amplifier adds to spacerequirements for preregulator 112 and adds to the bias currentrequirement, the power dissipation, and the heat generated bypreregulator 112.

To assure accurate performance of the operational amplifier,conventional integrated circuit design techniques require additionalmask steps and tighter tolerance controls for the fabrication processesinvolved as compared to the mask steps and process controls required forthe remainder of the integrated circuit. Additional mask steps andprocess controls add to the expense of integrated circuit manufacture,increase fabrication time, and decrease yield.

Some applications require integrated circuits having low operating andlow standby power consumption. In applications, including for example,portable computers, low power consumption is desirable while operatingand highly desirable while portions of the computer are idle. Thesummation of the bias current drawn by each integrated circuit in thecomputer is a significant continuous current drain on the battery. Biascurrents, therefore, contribute to limited battery operation, contributeto increased cost for sufficient battery supplies for particularapplications, and make some applications infeasible.

Thus, there remains a need for an integrated circuit design havingimproved voltage regulation circuitry characterized by lower biascurrent consumption. A design is needed for providing regulated voltageto the subcircuits of an integrated circuit while requiring less biascurrent, while occupying less area of the integrated circuit, whiledissipating lower power and generating less heat, and while respondingto abrupt changes in supply and load conditions without generatingunderdamped output voltage.

SUMMARY

Accordingly, an integrated circuit in one embodiment of the presentinvention includes a preregulator, a regulator, timing logic, and asubcircuit of the integrated circuit that uses regulated power. Theintegrated circuit receives an input power signal from an external powersupply.

The preregulator receives a flow of input current from the input powersignal and generates a reference signal. In one embodiment the referencesignal is developed from a stable voltage output from a band gapreference circuit. In another embodiment, the reference signal isdeveloped from the output of a charge pump.

The regulator regulates the input power signal using the referencesignal as a reference for regulation and thereby generates a regulatedpower signal for the subcircuit.

Timing logic determines when the regulated power is being adequatelyprovided and generates a control signal. The control signal is coupledto the preregulator. The preregulator is designed to respond to thecontrol signal by limiting the flow of input current to thepreregulator. In one embodiment, the preregulator includes two circuits:one circuit consuming lower bias current than the other. When thecontrol signal is received, the circuit consuming more bias current ispartially or completely disabled so that total bias current consumptionis reduced.

According to a first aspect of such an integrated circuit, thepreregulator includes an operational amplifier for high speed regulationof large in-rush currents and a series regulator characterized by lowbias current consumption. By disabling the operational amplifier afterinitial current requirements have been satisfied, the total operatingpower dissipation for the integrated circuit is reduced.

According to another aspect, an integrated circuit design incorporatingan operational amplifier in the preregulation circuitry can be designedand developed in less time because the functional requirements of theoperational amplifier are simplified.

According to yet another aspect, interference between the operationalamplifier and digital circuits on the integrated circuit is reduced whenthe operational amplifier is disabled. The design of the operationalamplifier is simplified because interference is less important.

According to another embodiment, a dynamic random access memory (DRAM)for operation from an external supply of about 5 volts includes apreregulator and regulator of the present invention for low powerconsumption. Functional circuits on the DRAM integrated circuit operateat a voltage about 3 volts. Lower total power consumption is achieved bysupplying internal voltage from a low power series regulator aftermeeting the need for supplying the internal voltage from a high poweroperational amplifier regulator.

The present invention may be practiced according to a method forreducing input power supply current from an input power signal suppliedto a subcircuit of an integrated circuit. The integrated circuitincludes a first preregulator and a second preregulator which operateswith less input power supply current than the first preregulator, aregulator, a charge pump, and a subcircuit. The method includes thesteps of: supplying power from the input power signal though the firstpreregulator to the charge pump until the subcircuit receives regulatedpower from the regulator; supplying power from the input power signalthrough the second preregulator to the charge pump; developing aregulator control signal at least in part responsive to the output ofthe charge pump; and supplying regulated power from the input powersignal through the regulator to the subcircuit in response to theregulator control signal.

According to a first aspect of such a method, by supplying the chargepump from the second stage of the preregulator, the first stage of thepreregulator is no longer necessary. Power consumption can, therefore,be reduced by ceasing to supply power from the first stage preregulator.When power is no longer being supplied by the first stage regulator, theflow of bias currents to the first stage preregulator can be limited ordisabled.

These and other embodiments, aspects, advantages, and features of thepresent invention will be set forth in part in the description whichfollows, and in part will become apparent to those skilled in the art byreference to the following description of the invention and referenceddrawings or by practice of the invention. The aspects, advantages, andfeatures of the invention are realized and attained by means of theinstrumentalities, procedures, and combinations particularly pointed outin the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a functional block diagram of an integrated circuit of thepresent invention.

FIG. 2 is a functional block diagram of the power regulation circuitryof a conventional integrated circuit.

FIG. 3 is a functional block diagram of a portion of the powerregulation circuitry of the integrated circuit of FIG. 1.

FIG. 4 is a timing diagram showing signals related to the powerregulation circuitry of FIG. 3.

FIG. 5 is a schematic diagram of a portion of the circuitry shown inFIG. 3.

FIG. 6 is a schematic diagram of operational amplifier A10 shown in FIG.5.

FIG. 7 is a diagram of a memory according to an embodiment of thepresent invention.

In each functional block diagram, a group of signals is shown as asingle line. A single line between functional blocks represents one ormore control or power signals. Signals that appear on several Figuresand have the same mnemonic are directly or indirectly coupled together.

In each timing diagram the vertical axis represents analog power andcontrol signal levels and binary logic levels; the horizontal axisrepresents time. Neither axis is drawn to scale. The vertical axis isintended to show the transition from active (asserted) to passive(non-asserted) levels of each logic signal. The voltages correspondingto the levels of the various analog and digital signals are notnecessarily identical among the various signals.

DESCRIPTION OF THE INVENTION

FIG. 1 is a functional block diagram of an integrated circuit of thepresent invention. Integrated circuit 10 is an integrated circuit havingconventional functions shown generally as circuit 30, and connectionsfor input power signals (VCCX) on line 42, ground signals (GND) on line44, an input shown generally as input signals on line 48 and an outputshown generally as output signals on line 58. The need for an outputsignal depends on the function of circuit 30. Line 58 may be deletedwhen the function of circuit 30 does not require provision of an outputsignal. As shown, circuit 30 uses power signals and control signals forinitialization and operation.

Power signals provided to circuit 30 are derived from power signals online 42. When circuit 30 requires multiple power signals for operation,integrated circuit 10 includes low voltage regulator 14 and primaryregulators 20. Low voltage regulator 14 provides intermediate powersignals on line 50, coupled as required to substrate charge pumps 16,special charge pumps 18, and primary regulators 20. Substrate chargepumps 16 provide power signals on line 52 coupled to circuit 30. Specialcharge pumps 18 provide power signals on line 54 coupled to circuit 30.Primary regulators 20 provide power signals on line 56 coupled tocircuit 30. When circuit 30 requires fewer power signals for operation,intermediate power signals on line 50 may be eliminated and relatedsimplifications may be employed as is well known in the art. Takentogether, signals on lines 50-56 provide operative power to circuit 30,enabling it to perform its intended functions.

Low voltage regulator 14 receives power and control signals on line 40provided by power up logic 12. Control signals on line 40 enable theoperation of low voltage regulator 14. Similarly, control signals online 46, provided by power up logic 12 enable the operation of substratecharge pumps 16, special charge pumps 18, and primary regulators 20. Thesequence of enablement of these several functional blocks depends on thecircuitry of each functional block and upon the power signal sequencerequirements of circuit 30.

The functions of power up logic 12 in another equivalent embodiment, notshown, are incorporated into threshold detectors and sequencing logic inlow voltage regulator 14, in charge pumps 16 and 18, and in primaryregulators 20. In one example of such an embodiment, charge pumps 18detect when power signals on line 54 are valid and supply a validitysignal to primary regulators 20. Primary regulators 20 include shuntcircuitry known to those skilled in the art to hold regulated powersignals on line 56 at ground until a predetermined time, for example,after validity signals are received from charge pumps 18.

In another equivalent embodiment of the invention, circuit 30 does notuse bias or power signals that would require a charge pump forgeneration. In such a case, substrate charge pumps 16 and special chargepumps 18 are not implemented; and reference voltages, if needed byprimary regulator 20, are provided by low voltage regulator 14.

FIG. 2 is a functional block diagram of the power regulation circuitryof a conventional integrated circuit. Refer to the background sectionfor a discussion of FIG. 2.

FIG. 3 is a functional block diagram of the power regulation circuitryof the integrated circuit of FIG. 1. Low voltage regulator 14 is shownin more detail whereas charge pump 18 and primary regulator 20 arecarried over from FIG. 1 in order to show interface signals in moredetail. Ground signal 44 is not shown explicitly but is coupled to eachfunctional block as is well known to those skilled in the art.

A charge pump of the type suitable for use in the circuitry shown inFIGS. 1, 3, and 5 is shown in U.S. Pat. No. 4,388,537, "Substrate BiasGeneration Circuit" to Kanuma, incorporated herein by reference. Thosehaving ordinary skill in the art will recognize that a buffer similar toU10 shown and described in reference to FIG. 5 can be added to theKanuma design for generation of the VALID signal.

Low voltage regulator 14 includes initial regulator 202, first stagepreregulator 204, and second stage preregulator 206. In general apreregulator is a regulator or a source whose output is used by anotherregulator. As a source, a preregulator generates a reference voltage orcurrent or generates a control signal, depending on design choices andthe needs of circuit 30. A regulator is a device that provides a signalcharacterized by a stable value. For example, a voltage regulatorprovides a signal having a voltage that is maintained between narrowtolerances, independent of supply and load variation. Thus, thepreregulating means of integrated circuit 10 includes low voltageregulator 14 and charge pump 18 because charge pump 18 provides avoltage VCCP as a reference to second stage preregulator 206, as will bediscussed below.

Low voltage regulator 14 receives input power signal VCCX on line 42. Inone embodiment, VCCX is a direct current voltage of 5 volts with acurrent supply capability of several hundred milliamps. VCCX powersinitial regulator 202 which generates bias voltage NBIAS on line 60 andreference signal VR on line 43. First stage preregulator 204 receivesinput power signal VCCX on line 42. When enabled by the ENABLE signal online 64, first stage preregulator responds to reference signal VR online 43 and bias voltage NBIAS on line 60 to generate a regulatedvoltage VCCRP on line 62. VCCRP supplies power to charge pump 18 andacts as a reference voltage for timing purposes to be discussed belowwith primary regulator 20. VCCRP in one embodiment is about 3.3 volts.

The ENABLE signal on line 64, when removed or not asserted, operates tolimit the flow of input current to first stage preregulator 204. In oneembodiment, first stage preregulator 204 is turned off so that it drawsno current from input power signal VCCX.

Second stage preregulator 206 receives input power signal VCCX on line42. In response to reference signal VR, second stage preregulator 206generates regulated voltage VCCRP on bus line 62 and regulator controlsignal VBIAS on line 66. Since the output of second stage preregulator206 is connected with the output of first stage preregulator 204, therespective output currents sum on bus line 62. Therefore, the currentdrawn from bus line 62 when first stage preregulator 204 is turned offis supplied entirely by second stage preregulator 206.

Charge pump 18 receives power signal VCCRP on bus line 62 to generateand maintain pumped voltage VCCP on line 54. When pumped voltage VCCPhas reached a stable condition, charge pump 18 generates the VALIDsignal on line 68. The stable value of VCCP depends on the design ofintegrated circuit 10. In one embodiment, for example, a voltage in therange -0.7 to -1.1 volts is output by a substrate charge pump. In otherembodiments the voltage output of special charge pumps are, for example,a voltage of 5.4 volts or a voltage about one VT (0.7 volts) above VCC.Pumped voltage VCCP is used by circuit 30 in one embodiment to maintainthe substrate below ground potential, in another embodiment to biasmemory word lines to a potential above the voltage of power signal VCCRon line 56, and in another embodiment as a regulated power signal tosatisfy the special bias and power requirements of circuit 30. Pumpedvoltage VCCP is used in the embodiment shown in FIG. 3 by second stagepreregulator 206 as a reference voltage for the development of the VBIASregulator control signal on line 66.

Primary regulator 20 receives input power signal VCCX on line 42. Inresponse to regulator control signal VBIAS on line 66, primary regulator20 generates regulated power signal VCCR on line 56. In one embodiment,VCCR is a voltage of about 3.3 volts with the capability to supplyseveral hundred milliamps of current to circuit 30.

Primary regulator 20 includes timing circuitry for generating the ENABLEsignal on line 64. In one embodiment, the timing circuitry is responsiveto the magnitude of the VCCRP voltage on 62, the magnitude of the VCCRvoltage on line 56, and the presence of the VALID signal on line 68. Inan equivalent embodiment, the ENABLE signal is developed from timingdelays measured from the application of input power signal VCCX. In yetanother equivalent embodiment, the ENABLE signal is developed inresponse to a combination of timing delays, signal detection, andmagnitude comparisons. The purpose of limiting the bias current drawn byfirst stage preregulator 204, and thus reducing input power supplycurrent to integrated circuit 10, can be accomplished in a preferredembodiment by turning off first stage preregulator 204 as soon as powersignal VCCR on line 56 initially reaches a stable condition. Thistechnique is preferred because it minimizes bias current consumption.Other embodiments that employ timing circuitry to accomplish thispurpose by generating or removing the ENABLE signal at other times areequivalent. Before describing a circuit embodiment of the process ofreducing input power supply current to integrated circuit 10, we nowturn to a timing description of that process.

FIG. 4 is a timing diagram showing signals related to the powerregulation circuitry of FIG. 3. After input power signal VCCX is appliedto integrated circuit 10 at time t1, the voltage increases to a stableoperating level at time t3. By time t2 the voltage of input power signalVCCX is sufficient for initial regulator 202 to begin generatingreference signal VR. The voltage of reference signal VR increases to astable operating level at time t4. By time t3, the voltage of referencesignal VR is sufficient for first stage preregulator 204 to beginraising the voltage on bus line 62 as represented by power signal VCCRP.By time t4, the voltage of power signal VCCRP is sufficient for chargepump 18 to begin generating regulated power signal VCCP. For theembodiment wherein VBIAS is generated responsive to VR and VCCP, secondstage preregulator 206 generates VBIAS beginning at time t2. The voltageof signal VBIAS increases to a stable operating level at time 16 whenthe voltage of regulated power signal VCCP has reached a stableoperating level. In response to regulator control signal VBIAS, primaryregulator 20 generates regulated power signal VCCR which reaches astable operating level at time t6. At time t7, charge pump 18 detectsthat its output, VCCP, is at a stable operating level and generates theVALID signal. In response to signal detection and magnitude comparisonsalready discussed in relation to timing circuitry included in primaryregulator 20, the ENABLE signal is generated at time t8.

Although the timing diagram represents the sequence of signals for oneembodiment, some variation of the sequence is within the scope of thepresent invention. For example, as will be understood by those of skillin the art, the response times of initial regulator, first and secondstage preregulator, charge pump, and primary regulator may vary with thecomplexity, capacitance, and drive capability of the respectivecircuitry so that the sequence of events between times t1 and t7 mayvary. In addition, the regulated power signals VCCP and VCCR may bewithheld from circuit 30 by shunt (clamp) circuits until each or bothhave reached stable operating levels, for example, at time t6. Becausethe time axis is not to scale, some of the events described in sequenceoccur simultaneously in equivalent embodiments.

FIG. 5 is a schematic diagram of a portion of the circuitry shown inFIG. 3. Reference signal VR is generated by a circuit, not shown, havinglimited current drive capability. In one embodiment, signal VR isdeveloped by a band gap reference circuit. For an explanation of bandgap reference circuits, see "A Precision Reference Voltage Source,"Karel E. Kuijk, IEEE Journal of Solid State Circuits June 1973. As asource for signal VR, other equivalent circuits are well known in theart for example circuits including an operational amplifier, adifferential amplifier, or a charge pump. Reference signal VR isfiltered by resistor R10 and capacitor C10 and applied to operationalamplifier A10. Operational amplifier A10 provides unity gain bufferingso that the output power signal VCCRP on line 62 has a voltagecorresponding to reference signal VR with increased current drivecapability. The current supplied by operational amplifier A10 isconducted on bus 62 to power charge pump 18.

Charge pump 18 generates regulated power signal VCCP at a pumped voltagelevel as described with reference to FIG. 3.

Resistors R12 and R14 operate as a voltage divider to provide the VBIASsignal on line 66 with a voltage between the voltage of VR and VCCP.Because both VR and VCCP have regulated voltage characteristics, thevoltage VBIAS is a regulated scaled result determined in part by thevalues of resistors R12 and R14. Thus, resistors R12 and R14 cooperateas means for scaling reference signal VR to provide regulator controlsignal VBIAS with a voltage between the voltage of reference signal VRand regulated power signal VCCP.

The VBIAS signal on line 66 controls the conductivity of transistor Q10so that the current passing through the source-drain channel isregulated. The gate of transistor Q10 is a so called control terminal oftransistor Q10. Transistor Q10, therefore, operates as a regulator,supplying current onto bus 62.

Bus 62 conducts current supplied by either or both amplifier A10 andregulator Q10. When amplifier A10 is disabled, current from Q10 suppliescharge pump 18 and the timing circuitry of primary regulator 20.

Transistor Q12 operates as a regulator in a manner identical to theoperation of transistor Q10. In an equivalent embodiment, regulatedpower signal VCCR is generated with a voltage different from the voltageof power signal VCCRP by connecting the gate of Q12 to an alternatesource of bias voltage as is well known in the art.

The ENABLE signal controls the operation of amplifier A10. The ENABLEsignal is generated by timing means shown in FIG. 5 as logic buffers U10and U12, and NAND gate U14. Buffer U10 outputs a logic levelcorresponding to whether VCCR exceeds a threshold voltage. In analternate embodiment, an analog comparator or level translator is usedin place of the logic buffer. The function of the buffer is to comparethe magnitude of the voltage of the VCCR signal to a threshold voltageand to generate an output binary logic signal as a result of thecomparison. The input validly differs from the threshold when, in thecase of positive input and threshold voltages the input is in excess ofthe threshold. Likewise, when the input and threshold voltages arenegative, the input validly differs from the threshold when the input isfurther negative than the threshold.

Buffer U12 operates in a manner similar to buffer U10, comparing themagnitude of the voltage of the VCCRP to a threshold voltage andgenerating an output binary logic signal as a result of the comparison.

NAND gate U14 combines the result of magnitude comparisons performed bybuffers U10 and U12 with the VALID signal on line 68, generated bycharge pump 18. The ENABLE signal is a high voltage until the signals onall three inputs to gate U14 are logic `1` whereupon the ENABLE signalis a low voltage. The effect of the voltage level of the ENABLE signalin a preferred embodiment is best understood with reference to theschematic of operational amplifier A10.

FIG. 6 is a schematic diagram of operational amplifier A10 shown in FIG.5. The circuit of operational amplifier A10 is a differential amplifierhaving balanced loads Q200 and Q210 which provide currents ib1 and ib2.The difference in input voltages on the gates of transistors Q220 andQ230 cause the ratio of these two currents to vary according to thedifference. These two currents sum to form current ib3, into a biascircuit formed in part by transistors Q240, Q250.

As shown in FIG. 5, the gate of transistor Q240 is coupled to the NBIASsignal on line 60, generated by initial regulator 110. Because Q250 isin series with transistor Q240 and current ib3 must pass throughtransistor Q250 in full, the ENABLE signal coupled to the controlterminal (gate) of transistor Q250, when at a low voltage will reducethe flow of current ib3. In a preferred embodiment, Q250 is turned offso that virtually no current passes through its source-drain channel. Byturning off transistor Q250, no bias current is drawn from input powersignal VCCX into operational amplifier A10. Thus, the total currentdrawn by integrated circuit 10 from input power signal VCCX is reducedby interrupting the flow of bias current to amplifier A10.

In an equivalent embodiment, the flow of bias current to low voltageregulator 14 shown in FIGS. 1 and 3 is limited by alternate limitingmeans including, for example, circuitry to pinch off the source-drainchannel of a regulator transistor, a load transistor, a biasingtransistor, or a similar control transistor; circuitry for coupling acontrol signal to the gate or an equivalent control terminal; orcircuits for coupling such a control signal to an additional gate of thesame device for the purpose of independent control. Equivalently, meansfor limiting current include switching devices for interrupting currentflow and back biasing circuits for increasing a voltage to interferewith current flow.

The transistor Q260 shown in FIG. 6 typically occupies an area about anorder of magnitude larger than the average size of transistors Q220through Q250. The large size is necessary for satisfying in-rush currentneeded by charge pumps. By operating amplifier A10 primarily during thetime before circuit 30 is powered and disabling amplifier A10 shortlythereafter, transistor Q260 can be located with less concern for signalinterference.

FIG. 7 is a diagram of a memory according to an embodiment of thepresent invention. Random access memory 324 provides data signal 326representing data stored at an address corresponding to address signal322. Random access memory 324 is powered by regulated power signal VCCP.Power signal VCCP supplies an elevated voltage to word lines in randomaccess memory 324.

A wide range of alternate embodiments are equivalent to the embodimentsdescribed above. For example, circuit 30 (a subcircuit of integratedcircuit 10) in alternate embodiments includes an analog circuit, a logiccircuit, a memory, a signal processor, a microprocessor, amicrocomputer, a signal converter (such as analog to digital, digital tosynchro, and the like), a device for communications, for processcontrol, for display, for monitoring safety conditions, or formonitoring conditions related to security. The benefit of reducing inputcurrent to an integrated circuit has primary application to batteryoperated systems, but has important applications in all systems formeeting energy conservation goals.

The foregoing description discusses preferred embodiments of the presentinvention, which may be changed or modified without departing from thescope of the present invention.

For example, P-channel FETs discussed above may be replaced withN-channel FETs (and vice versa) in some applications with appropriatepolarity changes in controlling signals as required. Moreover, theP-channel and N-channel FETs discussed above generally represent activedevices which may be replaced with bipolar or other technology activedevices.

Still further, those skilled in the art will understand that the logicalelements described above may be formed using a wide variety of logicalgates employing any polarity of input or output signals and that thelogical values described above may be implemented using differentvoltage polarities. As an example, an AND element may be formed using anAND gate, a NAND gate, or a wired-AND connection when all input signalsexhibit a positive logic convention or it may be formed using an ORgate, a NOR gate, or a wired-OR connection when all input signalsexhibit a negative logic convention.

These and other changes and modifications are intended to be includedwithin the scope of the present invention.

While for the sake of clarity and ease of description, several specificembodiments of the invention have been described; the scope of theinvention is intended to be measured by the claims as set forth below.The description is not intended to be exhaustive or to limit theinvention to the form disclosed. Other embodiments of the invention willbe apparent in light of the disclosure to one of ordinary skill in theart to which the invention applies.

The words and phrases used in the claims are intended to be broadlyconstrued.

A "circuit" or "subcircuit" refers generally to integrated circuits andincludes but is not limited to a packaged integrated circuit, anunpackaged integrated circuit, a combination of packaged or unpackagedintegrated circuits or both, a microprocessor, a microcontroller, amemory, a register, a flip-flop, a charge-coupled device, combinationsthereof, and equivalents.

A "signal" refers to mechanical and/or electromagnetic energy conveyinginformation. When elements are coupled, a signal can be conveyed in anymanner feasible in light of the nature of the coupling. For example, ifseveral electrical conductors couple two elements, then the relevantsignal comprises the energy on one, some, or all conductors at a giventime or time period. When a physical property of a signal has aquantitative measure and the property is used by design to control orcommunicate information, then the signal is said to be characterized byhaving a "value." For a binary (digital) signal, the two characteristicvalues are called logic "levels."

I claim:
 1. A voltage regulator for an integrated circuit device,comprising:a first regulator portion coupled to a power supply input ofthe device, said first regulator portion having a control input and afirst regulated voltage output; a reference voltage source having areference voltage output; a second regulator portion coupled to thereference voltage output, said second regulator portion having a secondregulated voltage output; and a regulator power reduction circuitcoupled to the control input and to the second regulated voltage output;wherein said regulator power reduction circuit substantially inhibitssaid first regulator from receiving current from the power supply inresponse to the second regulated voltage output achieving a minimumvalue.
 2. The voltage regulator of claim 1, wherein the fist regulatedvoltage output provides power to a first subcircuit of the device, andthe second regulated voltage output provides power to a secondsubcircuit of the device.
 3. The voltage regulator of claim 2, whereinthe second regulated voltage output further provides power to the firstsubcircuit when said first regulator portion is inhibited from receivingcurrent.
 4. The voltage regulator of claim 2, further comprising;acharge pump coupled to said first regulator portion, responsive to thefirst regulated voltage output to produce a third regulated voltageoutput.
 5. The voltage regulator of claim 4, wherein the secondregulated voltage output is enabled to provide power to the secondsubcircuit in response to the third regulated voltage output attaining avalid potential.
 6. A voltage regulator comprising:a current limitingcircuit; a preregulator coupled to a power source through said currentlimiting circuit; a control circuit coupled to said current limitingcircuit; and a primary voltage regulator coupled to said controlcircuit, wherein said control circuit is responsive to said primaryvoltage regulator to limit current flow from the power source to saidpreregulator.
 7. An integrated circuit device comprising:a first voltageregulator coupled to an input power source of the device; a firstcircuit coupled to said first voltage regulator; a second voltageregulator coupled to the power source; a second circuit coupled to saidsecond voltage regulator; a regulated power bus coupled to said firstcircuit and said second circuit; and a current limiting control circuitcoupled to said first voltage regulator and said regulated power bus,said current limiting control circuit adapted to restrict current fromthe power source to said first voltage regulator after a potential ofsaid regulated power bus achieves a valid value.
 8. The integratedcircuit device of claim 7, wherein said first circuit is a charge pumpwhich is adapted to pump a substrate of the device to a negativepotential.
 9. The integrated circuit device of claim 7 wherein saidfirst circuit is a charge pump which is adapted to provide a regulatedpotential, above a potential of the input power source, on saidregulated power bus.
 10. The integrated circuit device of claim 7,wherein the device is a microprocessor.
 11. The integrated circuitdevice of claim 7, wherein the device is a memory device.
 12. Theintegrated circuit device of claim 7, wherein restriction of current bysaid current limiting control circuit causes a reduction of heatproduction by the device.
 13. The integrated circuit device of claim 7,wherein restriction of current by said current limiting control circuitcauses a reduction of power consumption of the device.
 14. Theintegrated circuit device of claim 7, wherein said second circuitreceives a regulated operating supply voltage from said second voltageregulator in response to said current limiting control circuitrestricting current to said first voltage regulator.
 15. An integratedcircuit comprising:a voltage regulator, coupled to an external powersource, operable in a high power mode and a low power mode; and a chargepump coupled to said voltage regulator and to a regulated voltage powerbus; wherein said voltage regulator is operated in the high power modein response to the external power source, and said voltage regulator isoperated in the low power mode after said charge pump produces a validpotential on the regulated voltage power bus.
 16. The integrated circuitof claim 15, further comprising a memory array coupled to said chargepump.
 17. A voltage regulator comprising:a voltage reference circuitadapted to provide a reference potential; a charge pump adapted toprovide a regulated potential; a control circuit responsive to thereference potential and the regulated potential to provide a biaspotential; and a transistor coupled to an external power source and to aregulated power bus, said transistor responsive to the bias potential toprovide a regulated voltage on the regulated power bus.
 18. A voltageregulator for an integrated circuit, comprising:a first regulatorportion coupled to a power supply input of the integrated circuit, saidfirst regulator portion having a control input and a first regulatedvoltage output; a second regulator portion coupled to the power supplyinput, said second regulator portion having a second regulated voltageoutput; a charge pump having a third regulated voltage output; and aregulator power reduction circuit coupled to the control input and tothe third regulated voltage output; wherein said regulator powerreduction circuit enables said first regulator to receive current fromthe power supply in response to an invalid level of said third regulatedvoltage.
 19. The regulator of claim 18, further comprising:a regulatedpower bus coupled to the first regulated voltage output and the secondregulated voltage output; and a subcircuit coupled to said regulatedpower bus.
 20. A portable computer comprising:a battery; and anintegrated circuit comprising:a voltage regulator, coupled to saidbattery, operable in a high power mode and a low power mode; and acharge pump coupled to said voltage regulator and to a regulated voltagepower bus; wherein said voltage regulator is operated in the high powermode in response to a power signal of said battery, and said voltageregulator is operated in the low power mode after said charge pumpproduces a valid potential on the regulated voltage power bus.
 21. Anelectrical system comprising:a battery; a first voltage regulatorcoupled to said battery; a first circuit coupled to said first voltageregulator; a second voltage regulator coupled to said battery; a secondcircuit coupled to said second voltage regulator; a regulated power buscoupled to said first circuit and said second circuit; and a currentlimiting control circuit coupled to said first voltage regulator andsaid regulated power bus, said current limiting control circuit adaptedto restrict current from the battery to said first voltage regulatorafter a potential of said regulated power bus achieves a valid value.22. The electrical system of claim 21, wherein a memory device of thesystem comprises said first voltage regulator, said first circuit, saidsecond voltage regulator, said second circuit, said regulated power busand said current limiting control circuit.
 23. A method of supplyingregulated power to a circuit, comprising steps of:supplying current to ahigh power voltage regulator; generating a first regulated voltagethrough the high power voltage regulator; generating a second regulatedvoltage in a charge pump; generating a third regulated voltage;supplying the second regulated voltage to the circuit; detecting a validpotential level of the third regulated voltage; reducing currentsupplied to the high power voltage regulator in response to said step ofdetecting; and supplying the third regulated voltage to the circuit. 24.The method of claim 23, further comprising a step of:generating avoltage reference from a band gap reference circuit.
 25. The method ofclaim 23, wherein said step of supplying the third regulated voltage isperformed after said step of detecting a valid potential.
 26. The methodof claim 23 wherein the first regulated voltage and the third regulatedvoltage are each in a range of approximately 3 volts to approximately3.3 volts.
 27. The method of claim 23 wherein the third regulatedvoltage is greater than one threshold voltage above the first regulatedvoltage.
 28. An integrated circuit, comprising:a first regulator coupledto a power supply input of the integrated circuit, said first regulatorcoupled to a first regulated voltage bus; a charge pump adapted toprovide a pumped potential greater than a potential of the power supplyinput; a second regulator responsive to the pumped potential to supplycurrent to a second regulated voltage bus; and a low power regulatorcoupled to the first regulated voltage bus, wherein said low powerregulator provides a regulated voltage on the first regulated voltagebus in response to the pumped potential.
 29. The integrated circuit ofclaim 28, wherein current from the power supply input to the firstregulator portion is restricted in response to the pumped potential.